In recent years, the storage capacity of semiconductor memory devices, represented by a DRAM (Dynamic Random Access Memory), has increased. It is increasingly demanded that these devices can operate at higher speeds. The increase in storage capacity has been achieved by making memory cells smaller and by increasing the chip size. However, the miniaturization of memory cells is physically limited, and the increase in chip size leads to a reduction of yield and impairs an increase of operating speed.
To solve these problems fundamentally, there has been proposed a method such that a core unit having memory cells and an interface unit having peripheral circuits to the memory cells are provided as chips that are independent of each other, and a plurality of core chips can be allocated to one interface chip (see Japanese Patent Application Laid-open No. 2004-327474, Japanese Patent Application Laid-open No. 2005-191172 and Japanese Patent Application Laid-open No. 2006-13337). This can greatly decrease the size of each chip. In view of this, the method is expected to increase the storage capacity of semiconductor memory devices even more, while preserving high yield of the semiconductor memory devices.
Assume that the core unit and the interface unit are separate chips. The core chip and the interface chip can be fabricated in a memory process and a logic process, respectively. Generally, transistors made in the logic process can operate at higher speed than the transistors made in the memory process. Hence, if the interface chip is manufactured in the logic process, it can operate faster than the conventional interface chips. As a result, the interface chip enables the semiconductor memory device incorporating it to operate at high speed. Furthermore, the operating voltage of the interface chip can be lowered by about 1V, which helps to reduce the power consumption in the semiconductor memory device.
As described in Japanese Patent Application Laid Open No. 2004-327474, Japanese Patent Application Laid-open No. 2005-191172 and Japanese Patent Application Laid-open No. 2006-13337, the stereoscopic stacking of the plurality of semiconductor chips permits suppression of an increase in a packaging area on the printed circuit board.
In such a stacked semiconductor memory device, the core chips and the interface chips are connected through electrodes. The through electrode is an electrode arranged such that it penetrates a semiconductor substrate that configures the core chip or the interface chip. The through electrode has very small parasitic capacitance and parasitic inductance compared to a bonding wire, a TAB tape and the like. Thus, the through electrode can transfer a signal between the chips at very high speed. Another advantage is that, unlike the bonding wire or the TAB tape, the through electrode does not cause an increase in area in the planar direction, so that it greatly contributes to reducing the entire size of the stacked semiconductor memory devices.
Generally, one core chip is formed with a plurality of memory arrays (such as a memory bank), and one data through electrode is allotted the plurality of memory arrays. In other words, the plurality of memory arrays share one through electrode. For this reason, a simultaneous data transfer from the plurality of memory arrays (or to the plurality of memory arrays) by using one through electrode is not possible. The data transfer is only possible to one memory array in one operation.
On the other hand, a time during which an instruction is issued to access the memory array, the level of an internal bus is determined, and data is then read out from the memory array, or the data is written in the memory array, is subject to restriction of the reaction rate (4 to 7 ns) of the internal bus arranged within the memory array. When the core chip is a DRAM core, ten-odd ns are required. Thus, when the reaction rate (1 to 2 ns) of the through electrode, an output retaining period (1 to 2 ns) of the data, and the like are added, the limit of a data transfer cycle during which one through electrode is used is approximately 15 to 20 ns, and thus, it has been difficult to obtain a sufficient bandwidth.
In order to increase the bandwidth in the stacked semiconductor memory device, a plurality of memory arrays that do not share the through electrode can be probably operated in parallel. Accordingly, when the number of memory arrays included in one core chip is increased by segmenting the memory array included in one core chip, it becomes possible to further multiplex the parallel operation, thereby greatly increasing the bandwidth as a whole.
However, when the number of the memory arrays included in one core chip is increased, the number of through electrodes increases in proportion thereto. Therefore, an area occupied by the through electrode increases. This results in an increase in chip area, or in a decrease of a memory capacity. Another problem is that a defect occurs at a predetermined probability in the manufacturing of the through electrode, so that when the number of through electrodes is large, it is more probable that a defective through electrode is included in one core chip, thereby decreasing the yield.
Thus, in the conventional stacked semiconductor memory device, it has been difficult to increase a bandwidth while suppressing the number of through electrodes.